High Performance Vedic Approach for Data Security Using Elliptic Curve Cryptography on FPGA

Elliptic Curve Cryptography (ECC) is the best tool to provide security among all other standards. Performance of ECC is best as compared with Asymmetric algorithms, but not as good as the Symmetric Algorithms. Cryptographic implementations on FPGA provides hardware security advantage along with it. As we know ECC with dual point security is already a secured implementation with poor performance in terms of speed, area and power as compared with symmetric standards. So there is a trade-off between security and performance in terms of speed, area and power requirements. In this Paper, we provide efficient ECC approach for Cryptography with improvement in performance by replacing the conventional multiplier (16 bit) by Vedic multiplier (16 bit). Not only the performance improvement, but the proposed design recursively processes data in less area, less power consumption and with higher speed. The complete proposed design is synthesized and simulated using Xilinx 14.5 software and implemented on Spartan 3E FPGA Board. Proposed design show a remarkable improvement in area efficiency, time complexity, and power requirements when comparing with past implementations.