Realization of High Speed Low Power MCC Adder using Dynamic CMOS Transistors

Using multioutput domino CMOS logic, a cost effective implementation of Manchester carry chain (MCC) adder for 8-bit is designed in this paper. From this adder carries are generated parallelly employing two main carry chains of 4-bit. The suggested 8-bit adder module comprise confined length of carry chain. As a result of this ability, it is applied to realize broader adders and as well it guides to betterments in functioning rate equated to the related adders established upon the classical 4-bit MCC adder module.