Design and Implementation of 8 Bit Shift Register using Reversible Logic

Power dissipation is becoming major problem as device size is shrinking. Conventional circuits are irreversible in nature and dissipates power for every bit loss in circuit. Instead if we use reversible logic power dissipation can be reduced. The paper is intended to design and implementation of 8-bit shift register using reversible logic gates on FPGA board using chipscope. The proposed 8-bit shift register using reversible logic is optimized in terms of quantum cost, delay, number of logic gates used. Quantum cost of the proposed design shows up to 8% improvement and in comparison with existing work in survey. The coding is done using verilog module then simulated using Xilinx Modelsim and prototyped in Spartan6 board using real time tool chipscope for verification of result.