Novel Multilevel Inverter Design with Reduced Device Count

In this paper, a new topology for the multilevel inverter is proposed. Here, in this proposed topology we are using two well-known topologies as cascaded H-bridge multilevel inverter topology and combining it with multi-string multi-level inverter topology, and proposing a new multilevel inverter topology which is on the base reduced device count. The concept of Reduce device count is to reduce the size of hardware as well as cost and complexity of hardware. Here, with the help of this topologies, there is in the output we are able to make the thirty-one level and that too with the help of only ten switching devices and four dc sources. The operating details of strategy and system design of this proposed multilevel inverter system is described and verified by simulation results.