A cost effective architecture for HDTV with 2D/3D graphics

An integrated MPEG-2 transport demultiplexer and MP@HL video decoder and 2D/3D graphics core are presented. The described architecture integrates all digital decoding and graphics functions into one system, analog video encoding and decoding functions into other system and digital teletext/subtitling decoding functions and user or private data processing on a midrange performance host CPU (Pentium 200 MHz or MIPS 166 MHz). This results in the greater flexibility and reduction of hardware cost of digital set-top receivers.