Improved Performance of Single-phase and Two-Phase Enhanced Phase-Locked Loops by using Multiple Delayed Signal Cancellation Filters

The estimation of phase-angle, frequency and amplitude are crucial for the control of grid-connected power electronic systems in both single-phase and three-phase systems. The single-phase enhanced phase-locked loop (1P-EPLL) and two-phase enhanced phase-locked loop (2P-EPLL) techniques can be used to estimate single-phase and three-phase grid voltage quantities respectively. However, under the presence of harmonics, unbalance and dc offsets, the estimated quantities by these EPLLs may contain periodic ripples. Therefore in order to eliminate these periodic ripples multiple delayed signal cancellation (MDSC) filters are placed in the phase-angle estimation loop and amplitude estimation loop of these EPLLs. To improve the dynamic responses of MDSC based EPLLs, proportional-integral (PI) controller is replaced with a proportional-integral-derivative (PID) controller. The design guidelines for choosing the control parameters are provided. The MDSC filters in the EPLLs are realized both in direct-form and recursive-form structures. The proposed EPLLs are verified experimentally and compared with recent advanced EPLLs.