Clock Gating Techniques: An Overview

Clock gating is one of the most popular techniques used in many synchronous circuits for reducing dynamic power dissipation and it is helpful for decreasing the ability of power wasted by digital circuits. The major power consuming in electronics product is the systems clock signal and it is responsible for transition state of the components and this typically leads to the switching power consumption. Several techniques are used to reduce power some of the developed techniques are power gating, clock gating, adiabatic logic etc,. In clock gating technique, the unwanted clock signal is deactivated or blocked and by this activity, low dynamic power consumption can be achieved. Summary of issues associated with above clock gating techniques are presented for the research community to enable them to take future research in the right direction.