R3ToS based Partially Reconfigurable Data Flow Pipelined Network on chip

The incorporation of Data Flow Pipelining (DFP) along with the concept of Partial Reconfiguration (PR) in R3TOS based NoC is projected in this paper. Our research aims at including DFP in the router architecture to pipeline the data and reduces the latency by inserting “Slots” between the data based on the request channels. It processing a new input request at every clock cycle rather than waiting for all the data functions of input currently processing for the request to complete, resulting in increased throughput with shorter overall latency. The routing switch does so by parallel transmission of the data to the available slots before the previously allotted input completes the task. Implementation of adaptive routing in control logic after inspection of header data enhances this performance. Further, when partial reconfiguration is incorporated, the power consumption reduced up to 17% as its dynamically reconfigures the available topologies.