HW-based Architecture for Runtime Verification of Embedded Software on SoPC systems

Runtime verification provides a theoretical proved framework to synthesize monitors from formal specifications. At runtime, these monitors can be used to check that the execution of the system does not violate a security policy or a safety property. In this paper, we focus on the runtime verification of safety properties of real-time embedded software. For these systems, it must be ensured that monitoring does not jeopardize the scheduling. To do so, we use a hybrid hardware-software approach in the context of System-on-Programmable-Chip. A minimal instrumentation is added to the software to extract the execution trace. The verification is performed by hardware monitors on the FPGA. This implementation makes it possible to obtain a temporal overhead almost as low as a hardware implementation while allowing the use of efficient off-the-shelf platforms. The paper describes the architecture, its implementation, and shows results on a realistic case study.