Automated Generation of All-Digital I/0 Library Cells for System-in-Package Integration of Multiple Dies

This paper presents an automated cell library generation flow for all-digital I/O circuits for SiP integration. Given parameterized models of SiP wire traces, our method automatically designs, optimizes, and generates layouts of I/O cells for delay/energy minimization. We demonstrate that automated I/O library cell generation can reduce maximum die-to-die communication delay or energy for a given multi-die SiP design and associated interposer wire traces. The proposed flow is demonstrated considering 28nm CMOS technology and interposer based SiP integration.