A Distributed Functional Verification Environment for the Design of System-on-Chip in Heterogeneous Architectures

In complex System-on-a-Chip (SoC) projects, the conclusion of the project depends on the functional verification phase, which takes a long time. Synchronizing distributed and heterogeneous components in a functional verification environment might not be a simple task. This work aims to present a distributed verification environment that allows the integration of heterogeneous components. In this environment, it is possible to perform the functional verification of multiple components in heterogeneous architectures in parallel and distributed fashion. For this, an intercommunication framework already developed by the authors was used, based on the High Level Architecture (IEEE 1516) standard. Thus, this article also demonstrates how the proposed architecture abstracts communication and synchronization details to make the functional verification process in distributed components as straightforward as possible. As a demonstration of the developed solution, an experiment is presented with the functional verification of parallel algorithms in GPU and in FPGA, besides the verification using a CPU.