A Modular Architecture for the Semi-Automatic Design and Layout of Pipelined ADC Arrays

A modular architecture for Pipelined ADCs is proposed based on a simple unit cell. Given the cell and constraints, an optimized ADC can be designed, scaled, and laid out using software scripts. This enables a high-performance Pipelined ADC to be designed without the significant overhead of custom-designing each ADC stage, reducing design time. To demonstrate the architecture, a 24-channel, 12-bit, 25 MS/s ADC array for scientific imager readout has been implemented in 180 nm CMOS technology. The ADC array achieves input-referred noise of 190 μV-rms and crosstalk of less than -50 dB. The array dissipates 70 mW per channel.