Test results of the CHIPIX65 asynchronous front-end for the HL-LHC experiment upgrades

This work discusses the main results relevant to the characterization of an analog front-end processor designed in view of experiments with unprecedented particle rates and radiation levels at the High-Luminosity LHC (HL-LHC). The frontend channel presented in this paper is part of the CHIPIX65FE0 prototype, a readout ASIC designed in a 65 nm CMOS technology in the frame of the CERN RD53 collaboration. The prototype integrates a 64×64 pixel matrix, divided into two 32×64 sub-matrices with 50 μm pitch, embodying two analog front-end architectures based on synchronous and asynchronous hit discriminators. The analog chain takes an overall area close to 1000μm², with a per-channel power dissipation around 5 μW. The paper is focused on the characterization of the array with asynchronous channels, before and after exposure to ionizing doses up to 630 Mrad(SiO₂) of X-rays. The mean value of the equivalent noise charge (ENC), not significantly affected by radiation, is close to 90 electrons with no sensor connected to the front-end. The threshold dispersion before irradiation is 55 electrons, for a tuned threshold of 600 electrons, with a moderate increase after irradiation. The assessed performance guarantees sub-1000 electrons stable threshold operations, which is a mandatory feature for highly efficient readout chips for the HL-LHC.