FPGA Implementation of Pipelined 8×8 2-D DCT and IDCT Structure for H.264 Protocol

Discrete Cosine Transform (DCT) is the most widely used technique for image/video compression standards. In this paper, an FPGA based 8×8 forward Discrete Cosine Transform (DCT) and inverse Discrete Cosine Transform (IDCT) architectures are implemented for H.264 encoder and decoder respectively. It has been implemented using the pipelined structure for computing the Integer DCT and IDCT. The design is implemented without using any multiplication operation to reduce the complexity. H.264 is one of the recent video compression standards of the ITU-T Moving Picture Experts Group and Video Coding Experts Group. A pipelined architecture is used in this design to increase the speed of operation. The proposed resource effective architectures have been implemented and synthesized on xc2vp30 device that belongs to Vertex-2 Pro family. For Integer DCT architecture implementation, the resource utilization is 14% slices, 1% flip-flops, 11% LUTs, 51% 10Bs of xc2vp30 device and reaches an operating frequency of 520.996 MHz. For Integer IDCT architecture implementation, the resource utilization is 28% slices, 2% flip-flops, 24% LUTs, 37% 10Bs of xc2vp30 device and reaches an operating frequency of 525.22 MHz. In these designs, it takes only 49 clock cycles to generate the transformed outputs thus increasing the speed of operation.