Impact of Channel Engineering on Double Gate Junction Less Transistor for Improved Analog Performance

In this paper, the impact of channel engineering is explored on the device performance of double gate junction-less transistor (JLT). A source side n-type (5×10¹⁸cm^-3) pocket is used to improve the electrostatic integrity of conventional JLT device. Proposed JLT device improves the transport of electron from source to channel region more efficiently due to sharp rise in electrostatic potential compared with conventional JLT. Moreover, a reduction in drain electric field is observed, which improves reliability of proposed structure compared with conventional JLT. Proposed JLT device with high-k (C-WP-HfO₂) gate sidewall spacer shows significant improvement in the short channel effects compared with its conventional counterpart. C-WP-HfO₂ structure also shows impressive improvements in analog performance metrics such as transconductance (g_m), output conductance (g_ds) and unity gain cut-off frequency (f_T) compared with conventional JLT with HfO₂ spacers. Use of source side pocket also relaxes the requirement of high work function material for gate.