Cache Aware Dynamic Scheduler for Real Time Task in Multicore Processors

With the advent of SMT multicore (Simultaneous Multithreading) processors co-scheduling of jobs on the same core, thus sharing core resources like L1, L2 caches there results a per process performance degradation depending on process resource requirements and the resource contention induced byco-runners. The main constraint of real time schedulers is to meet task deadline. In this paper, we present a real time scheduling algorithm, Cache Aware Dynamic-Earliest Deadline First (CAD-EDF) for SMT multicore processors that ensures no deadline miss. To this end, the scheduler estimates the cache miss rate of each task and compares the cache miss and the slack time of each task with the task running in a core before assigning it to a core by which the deadline miss can be reduced. The performance of CAD-EDF scheduling algorithm has been implemented in LITMUS-RT kernel on a 64-bit Intel Xeon D-1548 processor with eight SMT cores and 16 logical processors. Experimental results on it shows that the proposed scheduler reduces the deadline miss and maximize the CPU utilization.