Comparative Analysis of a NAND Gate and a 2-Bit Magnitude Comparator Using GDI Technique

In this paper, an analysis of basic NAND gate using various CMOS techniques are discussed. These techniques include Pass Transistor Logic(PTL), Transmission Gate(TG), Domino Logic and Gate Diffusion Input(GDI). From these, GDI technique consumes less power. The power, delay and power delay product (PDP) are calculated. Later, using this low power GDI technique a Magnitude Comparator with 2-bit is compared with a proposed comparator. The proposed comparator is obtained by solving the truth table, using K-Map (Karnaugh Map). Here, the number of transistors needed is few and therefore the power dissipation gets decreased. Also, power, delay and PDP are calculated. Simulations are performed using Mentor Graphics Pyxis Tool in 180nmtechnology.