Insights Into the Impact of Pocket and Source Elevation in Vertical Gate Elevated Source Tunnel FET Structures

In this paper, we investigate a vertical gate-based elevated tunnel source (TS) FET structure with and without a vertical n+ pocket and compare its performance with a lateral p-n-i-n TS (LTS) FET. The lined arrangement of gate not only provides a performance boosting as expected but it further allows the flexibility to minimize the degradations at higher pocket doping using source elevation. The vertical gate and pocket alignment overcome the full-depletion constraint of the LTS FET and maintain a better subthreshold swing (SS) over a higher range of pocket doping and width. An optimized average SS as low as ~26 mV/dec is achieved over five decades of current which is improved by 58% and 67%, respectively, as compared to the LTS and p-i-n tunnel field-effect transistors (TFETs) with an on-current enhancement of one order and ~17×, respectively. Furthermore, the gate-to-drain capacitance (C_GD) in elevated source structures is a highly sensitive function of the pocket doping and can be significantly reduced by tuning the source elevation length L_CV at higher pocket doping. At the same pocket conditions, a one order reduction in C_GD is achieved with respect to the lateral configuration without compromising the intrinsic delay (C_GD× V_DD/I_ON). The circuit-level investigations show that due to the, otherwise, higher C_GD in the LTS FET, the switching delay remains unaffected by the on-current boosting caused by higher pocket doping. However, it is drastically improved by ~23% in elevated source structures at a change from 4 × 10¹⁹ to 5 × 10¹⁹/cm³. A faster switching delay(τ_p) of ~116 ps is achieved at a ~33% reduced device base area.