A Fractional-N Divider for Phase-Locked Loop with Delta-Sigma Modulator and Phase-Lag Selector

A fractional-N divider with delta-sigma modulator and phase-lag selector for phase-locked loop (PLL) is presented in this paper. Basically, the fractional-N frequency divider consists of a pre-divide-by-2 frequency divider (Div. 2), a phase selector (PS) with the auxiliary circuit, a multi-modulus frequency divider (MMD) and a delta-sigma modulator (DSM). With a 65nm CMOS process, the high speed circuit, like Div. 2, and low power circuits, like MMD and DSM, are designed. The proposed divider achieves 8.5GHz maximum operating frequency with 32-256 division range and less than 25 Hz frequency resolution. The divider power consumption is less than 8mA from a 1.2 V power supply at 6GHz.