The Quest of the Ideal Error Detecting Architecture: The GRAAL Architecture

Silicon-based CMOS technologies are fast approaching their ultimate limits. By approaching these limits, fabrication yield, reliability, and power densities, worsen steadily making further nanometric scaling increasingly difficult. These problems would become showstoppers in ultimate-CMOS and post-CMOS technologies, unless efficient fault-mitigation and low-power approaches are developed to maintain acceptable levels of yield, reliability, and power densities. This paper describes the GRAAL architecture, which improves significantly the fault detection efficiency, cost, and timing constraints of the double-sampling approach, providing this way an efficient scheme for solving the issues induced by aggressive technology scaling in the era of ultimate-CMOS and post-CMOS technologies.