Gate Driver Architectures Impacts on Voltage Balancing of SiC MOSFETs in Series Connection

In power converter configurations like multi-cell, multi-level, series connection of power devices etc. under very high switching speeds, several dv/dt sources generated at different floating points produce conducted EMI perturbations from the power part to the control part through the many gate driver circuitries. The modifications of the parasitic capacitive propagation paths between the power and the control sides have impacts on the circulating current produced by high dv/dt, which, in turns, affects the voltages distributions (static and transient) among the power devices. This paper presents news architectures for gate drivers power supplies implementations in series connection to minimize parasitic currents, especially reducing the common mode currents and to minimize the unbalance voltages of SiC-MOSFET devices in series connections. Simulations and experiments validate the advantages of the gate driver power supplies proposed architectures on the common mode currents and drain-to-source voltages of series-connected devices.