Identification And Controlling Sources Of Die Chippings On Wafer Level Chip Scale Package (Wlcsp) Process

With the technology gearing towards smaller and leaner packages, customers are now investing on a bare die and wafer level chip scale package (WLCSP) since this allows integration of wafer fab, packaging, test and burn-in at wafer level in order to streamline the manufacturing process undergone by a device from silicon start to customer shipment. Bare die packages or WLCSP process starts from fab, bumping house, wafer testing, wafer sawing, packaging and to the customer. Major challenges by most of the semiconductor industry is to control die chippings (active side, backside and side wall). High cost of investment is required on automatic inspection system to screen out die chippings. Automated outgoing inspection screens out top die chippings, while tape and reel requires 6 sides inspection (top, bottom and 4 sides). The objective of this project is to identify sources of die chipping and reduce if not totally eliminate die chipping thereby reducing the requirement of automated inspection system.