Die Pop Challenge and Comprehensive Solutions in Vacuum Reflow Technology for Semiconductor Packaging

Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) die thickness is getting thinner over time due to improvement of power efficiency in new advance power electronic packages. This has caused solder voids performance deteriorates as the result of die warping after thinning and caused die crack issue. Vacuum reflow is introduced to improve that solder void issue with the target of 5% or below from origin 20%. During the study, die pop challenge was encountered at vacuum reflow process. In this paper, the root cause and solutions of the die pop will be discussed. The challenge of this project is to achieve zero die pop defect while meeting 5% or below solder void sizes underneath warped die in high productivity mode condition. A thorough pressure profile optimization was conducted in meeting these requirements that always in contradiction between die pop and low void in limited vacuumed time condition at vacuum pressure profile. Optimizing vacuum pressure level with two steps profile and solder paste deposition volume are critical in achieving the goals.