Electrostatically-Doped Hetero-Barrier Tunnel Field Effect Transistor: Design and Investigation

In this paper, an electrostatically-doped hetero-barrier tunnel-field-effect-transistor (ED-Het-TFET) based on stepped broken-gap (type-III) is simulated, investigated, and compared with the conventionally-doped stepped broken-gap hetero-barrier TFET (Het-TFET). ED-Het-TFET employs GaSb source region, In_0.85Ga_0.15As-based channel-drain regions, and In_0.2Ga_0.8As as tunnel barrier, with a uniform p-type doping, done initially throughout the device layer. Two metal gates (c-gate and n-gate) with proper workfunctions are used to invert the doping in In_0.85Ga_0.15As layer to realize n-type channel-drain regions. A 2-D calibrated simulations have shown improvement in the OFF-state current and the $I_{\text {ON}}/I_{\text {OFF}}$ ratio. OFF-state current in the ED-Het-TFET has improved by more than an order of magnitude. Furthermore, transient analysis reveals that ED-Het-TFET performs on par with its conventional counterpart in terms of rise propagation delay during circuit level implementation. A high $I_{\text {ON}}/I_{\text {OFF}}$ ratio of ~ 10⁸ (average subthreshold slope of ~11 mV/decade) is obtained at 20-nm gate length for a very low operating voltage of 0.1 V, enabling it to be a device for future ultra-low power applications.