Observation of Solder Layers for PJVS Chips Formed with Supersonic-Soldering Method

The InSn solder layers between Si chips for programmable Josephson voltage standard (PJVS) and sapphire substrates for thermal contact were observed using a scanning acoustic microscope. The solder layers were formed with a supersonic-soldering method in several conditions. Based on the results of the observations, the void ratio in the solder layers was estimated to be approximately 20 % - 40 %, which is much improved in comparison to that obtained with a conventional soldering method of approximately 80 %. We are now trying to measure the influence of these soldering methods on the thermal contact of PJVS chips.