A reduced-power algorithm and VLSI architecture for sequential decoding

A new algorithm and associated VLSI architecture for sequential decoding of convolutional codes is described. Its error rate performance is found to be virtually identical to that of the classical stack algorithm, while the expected power consumption of the described VLSI implementation is found to be at least one order of magnitude smaller (depending on channel bit error rate) than that of a previously proposed architecture, for nearly the same decoding speed.