A low latency architecture for computing multiplicative inverses and divisions in GF(2/sup m/)

A low latency architecture to compute the multiplicative inverse and division in a finite field GF(2/sup m/) is presented. Compared to other proposals with the same complexity, this circuit has a lower latency and can be used in error-correction or cryptography to increase the system throughput. This architecture takes advantage of the simplicity to compute powers (2/sup i/) of an element in a Galois field. The inverse of an element is computed in two stages: power calculation and multiplication. A division can be performed using only one more multiplication in the inversion circuit.