Synthetic Laboratory Imitation of Transient Voltage Stresses of MMC-HVDC Links

Overvoltages occuring in High Voltage Direct Current (HVDC) links during pole to ground faults of Modular Multilevel Converters (MMC-HVDC) differ significantly from the normative switching impulse (SI) or normatively predefined slow front overvoltage waveforms. Knowledge on insulation system behaviour under consideration of those non-standard impulses is rare. However, for insulation coordination strategies of MMC-HVDC, this information gains in importance in order to determine insulation worst case stresses. For this purpose, a suitable and scalable laboratory test setup for the imitation of expected MMC-HVDC transient stresses is presented. Besides the presentation of a theoretically modelling approach and basic circuit design rules, a small scale laboratory realization is presented and obtained results are discussed. This setup is scalable and suitable for future investigations on related dielectric effects caused by those non-normative impulses.