IPplacer: An Efficient 0-1 Integer Programming Based Placement for VLSI Circuits

The placement phase is the most crucial in the physical design synthesis of Very Large Scale Integrated (VLSI) system for achieving design with optimized routability, wire-length, timing usage and power. Though placement comprises of three conventional approaches (e.g. global placement, legalization and detailed placement), we have only dealt with global placement which is the basis of other two phases in placement problem and is of great importance. With advancement in process technology and thus increased architectural complexity of circuits, the net list size of modern days VLSI design growing expeditiously, clustering for placement accelerated the placement process and provides better placement solution quality. To achieve good placement solution, a new clustering technique has been presented to segregate the nets into clusters based on the type of the circuit blocks and the connectivity among them. Meanwhile, a novel 0-1 Integer Programming (0-1 IP) based lookahead legalization process has been proposed for global placement with the help of a new force-directed method to create regions in order to reduce the searching space for global placement. Instead of implementing legalization separate, it is combined with the global placement phase which in turn reduces overhead of legalization. We have tested the performance of our proposed algorithms on ISPD 2011 benchmark circuits for mixed-size design. The obtained results are at par with all existing placers for mixed-size design w.r.t overflow reduction and wirelength except run time.