High-Speed Configuration Strategy for Configurable Logic Block-Based TCAM Architecture on FPGA

Ternary content addressable memory (TCAM)-based high-speed search engines are extensively used to accelerate applications in network routing. Researchers have used field programmable gate arrays (FPGAs) to implement TCAM-based classification engines. The existing RAM-based architectures of TCAM undervalue the massive parallelism capabilities of FPGA which is evident from their relatively high latencies. This paper presents an FPGA-based TCAM design which exploits the rich logic resources available on contemporary FPGAs for an increased throughput parallel implementation compared to existing designs. The encoded bits of the traditional TCAM table are stored in the flip-flop resources, and the comparison operation is performed using the look-up table resources of the slices of configurable logic blocks. The structure and simple mapping methodology of the proposed design enables the implementation of a high-speed update operation in only a single cycle. We implemented our proposed TCAM design on a Virtex-6 XC6VLX760 FPGA device. Our proposed design achieves almost 30 % better throughput compared to existing TCAM designs for FPGAs with an efficient utilization of FPGA resources.