A Novel Approach for Delay Variation Reduction in Domino Logic Gates using Keeper Circuit

In this paper, an easy approach for reduction of delay variations in domino logic circuits is proposed. The two main reasons for increase in delay variability of domino logic circuits are stated as process variability and closed loop formed between output inverter gate and keeper transistor. Thus, the proposed approach reduces loop gain of the closed loop formed, thereby reducing delay sensitivity to process variations. In particular, standard keeper circuit is modified and new keeper circuit is proposed with reduced loop gain which results in reduction of delay variations while keeping the same noise margin and area. Other performance parameters like delay, power and Power Delay Product (PDP) of proposed keeper are also compared with other circuits. All the circuits are designed using CADENCE Virtuoso tool at 90 nm technology and simulation is done using SPECTRE simulator.