Dual-k HfO2 Spacer Bulk Planar Junctionless Transistor for Sub-30 nm Low Power CMOS

In this paper, we propose the use of dual-k spacers to improve the electrostatic integrity and thereby scalability of bulk planar junctionless transistor (BPJLT). The proposed structure builds upon the idea of an isolated ultra-thin heavily doped device layer whose volume is fully depleted in the OFF-state and flat band in ON-state. Using extensive device simulations, we demonstrate that the use of high-k spacers improve the electrostatic integrity of both n-channel and p-channel MOSFETs. Further, due to fringing electric field through high-k spacer to the thin body layer the off-state leakage current (IOFF)), subthreshold swing (SS) and drain induced barrier lowering (DIBL) of the proposed n-channel and p-channel MOSFETs are reduced by ~60%, ~15% and ~30% respectively over the conventional BPJLT devices. In addition, the ION/IOFF ratio of the proposed devices is improved by ~55% over the conventional BPJLT devices. This clearly shows that, the proposed dual-k spacer BPJLT devices are most promising for sub-30 nm low power CMOS logic circuits.