Design And Implementation Of Low Power High Speed Flash ADC for UWB Applications

ADCs are the key design blocks and are currently adopted in many applications to improve digital systems, which achieve superior performance with respect to analog solutions. This paper proposes a low power design of high speed flash ADC of 3 bit, 4 bit and 8 bit and their comparison results. For 8 bit ADC, 255 comparators are used but in this design the number of comparators is decreased to 30 that decreases the area consumption as well as increases the speed. ADC has been designed in standard 0.18 μm using CMOS technology. The simulation has been done on cadence virtuoso. This type of design consumes 46 mW with the supply voltage of 1.8 V. It has wide applications in Ultra wideband as it works on 1.2 GHz frequency.