Dual-Mode CMOS Power Amplifier Based on Load-Impedance Modulation

This letter presents a dual-mode CMOS power amplifier (PA) that has an improved efficiency using load-impedance modulation in the low-power mode (LPM) and a fully differential operation in the high-power mode (HPM). For the LPM, the transistor in the negative path of the differential pair is turned ON, as a switch, to appropriately modulate the load impedance for the transistor in the positive path using the output balun. An external switch is deployed to turn VDD OFF for the negative path. In order to verify the proposed concept, a dual-mode CMOS PA IC was designed using a bulk CMOS process and an off-chip output balun, and it was evaluated using the 920-MHz narrow-band Internet of Things signal with a bandwidth of 200 kHz and a peak-to-average power ratio of 5.7 dB. For the HPM, the implemented PA exhibited a gain of 24.1 dB, a power-added efficiency (PAE) of 44.3%, and an adjacent channel leakage power ratio (ACLR) of -33.9 dBc at an average output power of 27.7 dBm. For the LPM, a gain of 19.3 dB, a PAE of 37.7%, and an ACLR of -34.9 dBc were obtained at an average output power of 21.7 dBm.