Designing of Efficient and Optimized Pre- Computational Based Content Addressable Memory

Many memory devices store and fetch the data from specific memory location but they require more time for fetching the data. To overcome such issue data needs to be accessed by their content rather than their address. A memory which accesses data in such a way is called the Content Addressable Memory (CAM). The motive of this research work is to combine various Pre-Computational Based CAM (PB-CAM) design methods which helps in optimizing both speed and area of the system. Also, it will help in deploying many applications in various fields such as data compression, fast lookup of routing, firewalls, switches, and routers. The result shows that the proposed parameter extractor circuit is low cost, faster and consumes lesser power. Further improvements in power consumption and speed can be done by combining various techniques such as gated block selection techniques, current race scheme etc. The PB-CAM architecture is implemented in 0.18um, 0.9um and 0.45um technology.