A Scalable VHDL-Implementation Technique of the Priority Encoder Structure into FPGA

The problem of scalable and optimal behavior-style description of the priority encoder into FPGA was examined. The structural synthesis technique of a scalable priority resolving circuits in sequential and parallel forms, which allow improving the FPGA resource utilization in comparison with typical description, was proposed. A novel approach of scalable synthesis of the triangular threshold-logic gate array was also proposed. The results of research and development, which have presented by structure generation circuit and algorithm, were confirmed by correct register-transfer level representation and during timing simulation. The numeric comparative assessments of FPGA recourses utilizing depending both the encoder inputs number, priority resolving circuit topology and threshold-logic gate unit was implemented.