Analysis and Design of Residue Number System Based Building Blocks

This paper deals with designing of RNS (Residue Number System) based building blocks for applications in digital signal processing. RNS provides parallel, carry free operations and since it deals with small numbers hence it is faster than other conventional methods. RNS based processing is performed in three stages namely Forward Conversion (FC), Modular Operations, and Reverse Conversion (RC). This paper is aimed at designing and analysis of efficient blocks in terms of area, delay and power for special moduli-set {2
ⁿ
−1, 2
ⁿ
, 2
ⁿ
+1} using std_cell at 32/28 nm technology.Modification is done in earlier proposed architecture of Forward Converter for making it work for all valid combination of input data. In all basic blocks, binary adder is main component. Verilog HDL is used to design different blocks. Synopsys design compiler is used for area, power and delay calculation at 32/28 nm technology. It is observed that CSA (Carry Select Adder) based reverse converter is approximately 20% faster as compared to that based on RCA (Ripple Carry Adder). Also we have compared LUT based design of two different types of reverse converter namely CRT (Chinese Reminder Theorem) and MRC (Mixed Radix Converter).