A Distributed Register File Architecture Based on Dynamic Scheduling for VLIW Machine

Distributed register files have the advantages of area and power compared with centralized register files in very long instruction word (VLIW) machine. But it may complicate the internetwork. A distributed register file architecture based on dynamic scheduling is proposed in our work. A portion of latency on internetwork is shifted to the latency among registers by latency transfer. And the decrease in the fanout of writing ports leads to a reduction in the power of the internetwork. To ensure the external compatibility of the distributed register file interface, the register was redirection designed. A dynamic scheduling strategy is designed to avoid conflicts between physical entities and logical entities that redirect registers. The optimization was evaluated on our in-house processor. The register file based on distributed dynamic scheduling reduces 15.48% of latency. The system frequency is raised from 1.19 GHz to 1.41 GHz. The power decreased by 27.42%.