Analysis and Design of a High Gain CMOS Low Noise Amplifier for UWB Communication in 180 nm and 90 nm CMOS Processes

In this paper, a low power high gain ultra-wideband (UWB) CMOS low Noise amplifier (LNA) is proposed. The new structure adopts a two-stage common-source (CS) amplifier. The first stage is based on an inverter-biased amplifier with resistive feedback to provide wideband input matching and low noise figure (NF). The second stage enhances power gain and achieves output matching. The LNA is simulated using both TSMC 180 nm and 90 nm CMOS processes. Simulated results in a 180 nm show that the NF is less than 2.6 dB, the power gain is 11.2-13.8 dB, and the input return loss is better than −11.7 dB in the range of 3 to 10 GHz. Simulated results in a 90 nm exhibit that the NF is less than 3.4 dB, the power gain is 10.85-11.85 dB, and the input return loss is better than −10.54 dB over 3 to 10 GHz. The LNA consumes 13.19 mW from a 1.8-V supply voltage and only 5 mW from a 1-V supply voltage in 180 nm and 90 nm technologies, respectively.