BIST-Based Online Test Approach for SRAM-Based FPGAs

FPGA chips have wide applications in nowadays digital systems. Because of fault prone nature of FPGA chips, their testing is one of the major challengs for designers. Among various test methods, the Built-in Self- Test (BIST) based approaches have shown good performance. In this paper, an efficient online and non-concurrent method is proposed to test and detect faults in FPGA which preserves initial values of SRAM cell. Furthermore, the test process does not need additional reconfiguring and test of each configurable logic block has been done in 16 clock cycles. The proposed BIST architecture has been simulated in HSPICE based on 45-nm CMOS technology. Simulation results indicated 100% coverage for single stuck at faults along with 59% area overhead due to additional BIST hardware.