Research on Cell Timing Modeling Based on FPGA Cell Configurations

This paper is a study of cell timing modeling method used in STA(Static Timing Analysis) module of EDA(Electronic Design Automation) tool. In the design of ASIC(Application Specific Integrated Circuit), cell timing is modeled using the Synopsys Liberty cell library format. But it is not very suitable for FPGA. On the one hand, cell timing modeling with Liberty format can not describe timing changes caused by different cell configurations. On the other hand, Liberty format method contains many ASIC-specific features that are not useful to FPGA. Model cell timing for FPGA with Liberty format may cause unnecessary development errors. Therefore, this paper proposes a cell timing modeling method based on FPGA cell configurations. In this paper, two methods are used to model cell timing for several logic cells in FPGA. During the parsing of cell timing library, a specific memory monitor is used to monitor cell timing modeling results for each cell. Record and compare the size of memory required for cell modeling results, demonstrating the simplicity and efficiency of cell timing modellna based on FPGA cell configurations.