Design of a Low-Power Ultra High Speed Dynamic Latched Comparator in 90-nm CMOS Technology

Fast operative comparator design in CMOS technologies is challenging work at low supply voltage. In this paper, a new design of a low power ultra-high-speed dynamic latched comparator has been proposed for ADCs and bioimplantable circuits, by trade-off between speed and power. In this proposed comparator, a NAND latch circuit has been used in the latching stage which results in both high-speed operation and low power dissipation. An analytical expression ensure that the delay time is significantly decreased. Simulation results in Cadence Virtuoso Analog Design Environment exhibit that proposed comparator consumes only 8.42 μW per conversion and 224 ps time delay at 0.8 V supply. Maximum clock frequency is achieved 4 GHz at 0.8 V supply. In comparison, 38.98% of power consumption and 62.56% of time delay of conventional double-tail dynamic latched comparator ensure the better performance of the proposed comparator.