Evaluation of an Artificial Neural Network Approach for Timing Modeling of CMOS Gates

The development of reliable and fast timing models for CMOS logic gates is a significant task for the IC technology. Analytical approaches have been proposed to accelerate timing analysis while keeping the accuracy in acceptable levels. However, the complexity of the analytical modeling procedure increases as we are moving towards new technology nodes influencing mostly the provided accuracy. The artificial neural network (ANN) approach could be a solution to this complexity. In this paper, the use of ANNs for timing modeling of CMOS gates is evaluated. Several different ANNs schemes are developed, optimized and studied regarding their accuracy, resource requirements and speed. Moreover, we design a new training method by combing the Particle Swarm Optimization (PSO) a meta-heuristic algorithm in conjunction with the Levenberg-Marquardt (LM) backpropagation algorithm. The outcomes show that the new training method obtains better results that the LM algorithm. The efficiency of adopting a common neural network structure, letting the coefficients to distinguish between the different logic gates is investigated.