Compact Automatic Metal Routing Algorithm in DSM technologies

Today's miniaturisation of devices and many of foundries are fabricating the IC's in 20nm and 14nm technology like INTEL, TSMC. 20nm and 14nm is a drastic shrinking in silicon size called deep submicron technology (DSM) which are driving most of the today's products like mobile phones, laptops. With the introduction of DSM technologies there is a huge impact on routing because of increased numbers of transistor and eventually space of routing. There are various CMOS design tools which can convert a design into a layout and efficient routing. One of such program is MICROWIND which has inbuilt placement and routing tool and algorithms to place and interconnect transistors using various metal layers in DSM technologies. To increase the performance for such routing, higher number of metal layers can be used in physical design layout and such features should be introduced in a EDA tool in accordance with technology rules. This paper focuses on optimizing routing algorithm used by MICROWIND to efficiently perform routing, reducing load on routing space. By using this feature we can reduce the delays, interconnect length, routing pitch and area on chip.