On the Hardware Implementation of a Reduced Complexity UFMC Chain

UFMC is a candidate waveform technology for 5G wireless systems and beyond. It combines the simplicity of OFDM with the advantages of FBMC. However, these advantages come together with an increase in the complexity at the transmitter caused by the implementation of a filter and applying an FFT for each sub-band, where as the receiver it is due to doubling the size of the FFT being implemented. In this paper, the computational complexity of UFMC receiver with FFT pruning is evaluated. In addition, both the un-pruned FFT and pruned FFT with inputs\outputs sparsity vector, as the case of UFMC receiver, are implemented on FPGA. The simulation and post-synthesis results show that the UFMC receiver complexity can be reduced to be similar or even less than OFDM. This complexity reduction of the UFMC receiver comes without performance degradation since no computational approximation is introduced.