On redundancy-modified NAND multiplexing

In order to make systems that are based on unreliable components reliable, the design of fault tolerant architectures will be necessary. Inspired by von Neumann's negative AND (NAND) multiplexing and William's interwoven redundant logic, this paper presents a fault tolerant technique based on redundancy-modified NAND gates for future nanocomputers. Bifurcation theory is used to analyze fault tolerant ability of the system and the simulation results show that the new system has a much higher fault tolerant ability than the conventional multiplexing based on NAND gates. According to the evaluation, the proposed architecture can tolerate a device error rate of up to 10-1, with multiple redundant components. This fault tolerant technique is potentially useful for future nanoelectronics.