Contact Metallization for Advanced CMOS Technology Nodes

Continuous CMOS scaling is being driven by innovation of novel device architectures to improve device performances at lower power consumption [1]. However, middle-of-the-line (MOL) continues to be a key performance and yield detractor for scaling. To alleviate these challenges, disruptive MOL architectures and materials are being proposed. At the ≤ 10NM node, significant differences are already seen in the MOL architecture and materials used by leading semiconductor companies [2]–[4]. This is expected to continue to smaller CMOS nodes where contacts represent significant contribution to external resistance (Rext). Figure 1 illustrates the impact of scaling on source/drain (S/D) contact vertical resistance, which can be quantified as the sum of silicide contact resistance (R
C
) and trench metallization resistance (R
Ts
) [5]. It can be observed that at ≥ 20 nm trench bottom critical dimension (BCD), silicide contact resistance is the predominant contributor to the total vertical resistance. At these dimensions, it is critical to lower the specific contact resistivity
$(\mathsf{p}_{\mathrm{C}})$
to reduce the vertical resistance. At narrow (< 20 nm) dimensions, it is observed that trench metallization resistance (for
$\mathsf{p}_{\mathrm{C}}=0)$
contribution to the total vertical resistance starts to increase. In addition, below ~11 nm of BCD we see an inflection in resistance because of the change in transport from high resistive nucleation layers to liner/barrier materials. It should be noted that this figure was generated using resistance calculations for a simple trench dimension not specific to any technology and typical MOL materials.