Fault Isolation of 2.5D and 3D Packages through Analysis Across Entire System

The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, real-estate management and faster connections has pushed the industry to develop complex 2.5D and 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die packages. The high level of functional integration and the complex package architecture in these, pose a significant challenge for conventional Fault Isolation (FI) and Failure analysis (FA) methods. Various FA tools available the industry provide key data for the fault isolation in packages. Very often, one need to correlate the package level results from tool across the entire system for accurate fault isolation. This means, the results must be taken across the system and perform analysis at each level in the system. In this paper, we are presenting case studies for different methods to perform analysis across the system for accurate fault isolation.