Analysis on Self-Heating Effects in Three-Stacked Nanoplate FET

In this paper, self-heating effects (SHEs) in three-stacked nanoplate FETs were investigated through the TCAD simulation. In order to obtain high reliability, the evaluation of SHEs was performed after ${I}_{D}$ – ${V}_{G}$ curve fitting based on the experimental data. First, general analysis on SHEs was conducted to confirm the influence of SHEs to electrical characteristics. The optimized nanoplate width for great electrical properties was proposed by using the figure-of-merit factor under the consideration of SHEs. In addition, difference of heat flux between FinFET and stacked nanoplate FET was analyzed. Based on the analysis, the two-step thermal resistance ( ${R}_{\text {th}}$ ) model depending on drain voltage was proposed. The two-step ${R}_{\text {th}}$ model in the stacked nanoplate FET matched well with the Berkeley short-channel IGFET model—common multigate model compared the other ${R}_{\text {th}}$ models. A seven-stage ring oscillator with the proposed ${R}_{\text {th}}$ model was demonstrated, and SHEs in the circuit level were confirmed.