Overhead Requirements for Stateful Memristor Logic

Memristors are being explored as a potential technology to replace CMOS for logic-in-memory systems that exploit the memristive non-volatility. Memristors are two-terminal, non-volatile device that exhibit a variable resistance that is dependent on the applied voltage history of the device, providing the capability to store and process information within the same structure. The ability of memristors to perform logic has been previously demonstrated, but previous analyses of memristor logic efficiency have not included the overhead CMOS circuitry that is required to control memristor logic operations. In this paper, the required overhead CMOS circuitry for implementing logic with memristors is evaluated for standard logic gates and a one-bit full adder to enable an analysis of the overall system efficiency. The results show that the number of CMOS devices in the overhead circuitry can be upwards of 50 times that of a conventional CMOS implementation, and that the power-delay product of the memristor logic with overhead circuitry is roughly one billion times greater than for conventional CMOS circuits. These results enable the conclusion that the overhead circuit requirements for stateful memristor logic threaten to negate any efficiency improvements that are achieved by the memristors themselves.